This invention relates to circuits and methods for controlling output discharge current. More specifically, this invention relates to integrated clamping circuits and techniques for controlling output discharge current from an external Field Effect Transistor (hereinafter xe2x80x9cFETxe2x80x9d).
Any integrated circuit that controls an external FET should, and often does, include protection for the FET gate. This protection is needed to limit the voltage differential across the gate dielectric. Excess voltage differential across the gate dielectric may cause oxide breakdown which, in turn, may lead to subsequent failure of the FET.
One conventional method of providing this protection is to connect a discrete zener diode between the source and the gate of the external FET. FIG. 1 shows a conventional zener diode-clamped circuit 100. Circuit 100 includes FET 110, board capacitor 120, zener diode 130, discharge transistor 140 and current source 150.
Zener diode 130 performs two functions in this circuit. First, zener diode 130 clamps the Vgs (gate-source) voltage in the positive directionxe2x80x94i.e., when the gate has a higher potential than the sourcexe2x80x94at the zener breakdown voltage (typically between about 8 volts and 20 volts). Second, it clamps the voltage in the negative directionxe2x80x94i.e., when the gate is lower than the sourcexe2x80x94at the forward diode voltage (typically between about 600 millivolts and 800 millivolts).
This conventional architecture, however, creates certain problems. For example, when an external diode is used to clamp the output in a negative directionxe2x80x94i.e., when Vgate drops below Voutxe2x80x94gate discharge transistor 140 conducts heavily to discharge the gate voltage of FET 110 and the capacitance on capacitor 120. This heavy conduction creates the possibility of thermal overload of discharge transistor 140. Thermal overload of discharge transistor 140 occurs more readily when there is a large capacitance on the output and/or a high Vout, because there is more energy stored in the output capacitor.
It would be desirable to provide integrated clamping circuit and techniques that discharge FETs and/or large capacitances without overloading discharge devices.
It is an object of the invention to provide integrated clamping circuits and techniques that discharge FETs and/or large capacitances without overloading discharge devices.
One embodiment of a method, according to the invention, for clamping the gate to source voltage of a FET during discharge of the output capacitance of a circuit, which output capacitance may include the capacitance of the FET and the capacitance of an output capacitor, in order to prevent oxide breakdown is as follows. The FET preferably has a gate coupled to an output capacitor. The method includes preferably discharging the FET using a relatively large drive current until the FET is OFF. When the FET is OFF, the method preferably includes providing a feedback signal to reduce the drive current by at least an order of magnitude. When the drive current is reduced, the method preferably includes discharging the output capacitance using the reduced drive current. Finally, the discharging preferably clamps the gate to source voltage of the FET at a pre-determined value.
A circuit according to the invention for discharging an output capacitance, the output capacitance including a gate capacitance of a FET and a distributed board capacitance coupled to the FET source, preferably includes a controllable current source that produces a drive current, the drive current preferably being adapted to partially discharge the gate capacitance and to shut the FET OFF, a clamp circuit that preferably produces a feedback signal during at least a portion of a time that the FET is OFF, this feedback signal preferably causing the drive current to be reduced, the reduced drive current that preferably discharges the stored capacitance. The drive current is preferably regulated at least partially by the feedback signal such that the gate to source voltage of the FET is maintained above a pre-determined minimum value.